As a result of the progress in the miniaturized processing technology, the tendency is more and more towards a large memory capacity of an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory) and an information storage device exploiting the semiconductor technology, such as a non-volatile memory having a floating gate or a charge capture film. In addition to the SRAM and DRAM, information storage devices of various types, such as MRAM (Magneto-resistive Random Access Memory), PRAM (Phase-change Random Access Memory) or RRAM (Resistance Random Access Memory), are being developed.
Before shipment of semiconductor elements, used for these information storage devices, the semiconductor elements are put to a test to confirm whether or not the products (semiconductor elements) will operate under predetermined conditions. It is only when the results of the test indicate that the products operate normally, the products are sorted as good products and shipped. By so doing, those products manufactured but determined to be rejects are prevented from being shipped.
The above test is usually carried out under an extreme condition within a range of use conditions that may be anticipated from the design specifications, that is, within a range of conditions in which a product in question is to be used. Such an extreme use condition is termed a worst condition or a corner condition. For example, in carrying out the test, the ambient temperature is set at a highest or lowest value anticipated, while the power supply voltage is set at a highest or lowest value anticipated. By so doing, it can be assured that a product shipped will operate normally under an arbitrary use condition comprised within the range of use anticipated.
The test is often carried out at more than two worst conditions, which correspond to different combinations of the temperature and the power supply voltage. This is because there is usually a plurality of failure modes of the information storage devices, such as failures in read out mode or those in write mode and, for these failure modes, failures are most likely to occur in the combinations of different temperatures and power supply voltages. That is, the worst conditions may differ for each of the failure modes.
The above test may be conducted under a condition severer than the worst use condition specified by the design specifications. For example, if the lower limit voltage of the design specifications is 1.0 V, the test may be conducted at 0.9V. Patent Document 1 discloses an example of such severe test, intended to remove products with only small operational margin to improve the reliability of the shipped products.
Patent Document 3 discloses a test method in which a voltage is applied to a pad of a semiconductor chip to render it difficult to read out data of DRAM cells to detect a memory cell with a small operational margin as a faulty cell.
As for an information storage device, only such a device in which all of the bits operate normally in a test is sorted as being a good product. In some cases, an information storage device has, in addition to the number of the above mentioned memory bits (the nominal number of bits stated in the design specifications), spare superfluous memory bits (redundant bits) in its inside, in which case the number of existing bits is larger than the nominal number of bits. If, in the information storage device, having these redundant memory bits, some of the memory bits have failed, they may be replaced by normal spare bits so that the nominal number of bits as specified in the design specifications will perform normal operations. The product in question may then be shipped as being a good product.
In Patent Document 2, there is disclosed a test method for a non-volatile storage device, having redundant bits, wherein, if the number of faulty bits out of the nominal number of the memory bits is not more than a preset number, the storage device in question is determined to be a good product for the time being, based upon a presupposition that the faulty bits can be rescued by the redundant bits after shipment.
As the size of the semiconductor element is scaled down, variations in device characteristics ascribable to a noise source inside the device increase. As typical of such noise is random telegraph noise (RTN), which pertains to a phenomenon that, with repetition of the process of electrical charges being captured into and released from trap sites in an insulation film of an MOS transistor, the transistor characteristics are varied discontinuously with time. It is stated in Non-Patent Document 1 that, with a semiconductor device exploiting a semiconductor element with a scaled-down size, there is an increasing risk of malfunctions of the semiconductor device ascribable to RTN. As another noise inherent to a semiconductor element, there is known a 1/f noise. It is generally accepted that this 1/f noise and the RTN have a common origin, and that the 1/f noise occurs by superposition of multiple RTNs.    [Patent Document 1] JP Patent Kokai Publication No. JP-A-5-120874, which corresponds to U.S. Pat. No. 5,309,399.    [Patent Document 2] JP Patent Kokai Publication No. JP-P2002-358795A, which corresponds to US Patent Application Publication No. US2004/0145939A1.    [Patent Document 3] JP Patent Kokai Publication No. JP-A-5-144296, which corresponds to U.S. Pat. No. 5,377,152.    [Non-Patent Document 1] K. Takeuchi et al., “Single-Charge-Based Modeling of Transistor Characteristics Fluctuations Based on Statistical Measurement of RTN Amplitude”, in Symposium on VLSI Technology, pp. 54-55, 2009.